The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device that can stably precharge bit lines in a bank interleave mode.
FIG. 1 is a block diagram of a conventional semiconductor memory device.
Referring to FIG. 1, the conventional semiconductor memory device includes upper unit memory cell arrays 10, lower unit memory cell arrays 20, bit line sense amplifier arrays 30, and sub hole regions 40. The bit line sense amplifier array 30 is shared by the upper unit memory cell array 10 and the lower unit memory cell array 20 and senses and amplifies data of a selected array. The sub hole region 40 controls the driving of the bit line sense amplifier array 30.
FIG. 2 is a circuit diagram of the upper and lower unit memory cell arrays 10 and 20, the bit line sense amplifier array 30, and the sub hole region 40 in the conventional semiconductor memory device of FIG. 1.
Referring to FIG. 2, the upper and lower unit memory cell arrays 10 and 20 include a plurality of unit memory cells each having a capacitor C1 for storing data in a smallest unit, and a transistor TR1 for transferring the data stored in the capacitor C1 to a bit line pair BL and /BL in response to a voltage of a word line.
The bit line sense amplifier array 30 includes a bit line sense amplifier 31, a first transfer unit 32, a bit line precharge unit 33, upper and lower selectors 34 and 35, upper and lower equalizers 36 and 37, a driving voltage generator 38, and a driving line initializer 39. The bit line sense amplifier 31 senses and amplifies a voltage difference of the bit line pair BL and /BL. The first transfer unit 32 transfers data applied on the bit line pair BL and /BL to a data bus pair SIO and /SIO in response to a column select signal YI. The bit line precharge unit 33 precharges the bit line pair BL and /BL in response to a bit line precharge signal BLEQ. The upper selector 34 connects one of the upper unit memory cell arrays 10 to the bit line sense amplifier 31 in response to an upper bit line separate signal BISH, and the lower selector 35 connects one of the lower unit memory cell arrays 20 to the bit line sense amplifier 31 in response to a bit line separate signal BISL. The upper and lower equalizers 36 and 37 equalize the levels of the bit line pair BL and /BL in response to the bit line precharge signal BLEQ. The driving voltage generator 38 generates driving voltages RTO and SB of the bit line sense amplifier 31. The driving line initializer 39 precharges and equalizes the driving voltage lines in response to the bit line precharge signal BLEQ.
Further, a second transfer unit 52 transfers data applied on the data bus pair SIO and /SIO to a local data bus pair LIO and /LIO. A main amplifier 54 senses and amplifies the data applied on the local data bus pair LIO and /LIO and outputs the amplified data to a global data bus pair GIO and /GIO. The second transfer unit 52 and the main amplifier 54 are disposed within a peripheral region.
The block for generating the bit line precharge signal BLEQ will be described below in more detail.
FIG. 3 is a circuit diagram of a bit line precharge signal generator in the conventional semiconductor memory device of FIG. 1.
Referring to FIG. 3, the semiconductor memory device includes a precharge control signal generator 60 and a driver 70. The precharge control signal generator 60 is configured to receive flag signals LAX9A and LAXBC to output a precharge control signal BLEQB. The driver 70 is configured to drive the bit line precharge signal BLEQ in response to the precharge control signal BLEQB.
Upon operation of the semiconductor memory device, the precharge signal generator 60 deactivates the precharge control signal BLEQB to a logic high level when the flag signals LAX9A and LAXBC having information on the selection of the corresponding bank are activated. The driver 70 deactivates the bit line precharge signal BLEQ to a logic low level in response to the precharge control signal BLEQB.
The bit line pair BL and /BL becomes a floating state because the bit line precharge unit 33 is disabled in response to the bit line precharge signal BLEQ of the logic low level. The driving line initializer 39 sets the driving voltage lines RTO and SB to a floating state in response to the bit line precharge signal BLEQ.
When the flag signals LAX9A and LAXBC are deactivated, the precharge control signal generator 60 activates the precharge control signal BLEQB to a logic low level. The driver 70 activates the bit line precharge signal BLEQ to a logic high level in response to the precharge control signal BLEQB.
The bit line precharge unit 33 of FIG. 2 is enabled in response to the bit line precharge signal BLEQ of a logic high level and thus the bit line pair BL and /BL is maintained at a precharge voltage VBLP. The equalizers 36 and 37 of FIG. 2 controls the connection of the bit line pair in response to the bit line precharge signal BLEQ such that the same voltage level is maintained.
When an active command is inputted, the bit line precharge signal BLEQ makes the bit line pair BL and /BL and the data bus pair SIO and /SIO set to a floating state. Thus, the bit line sense amplifier can sense and amplify the data transferred from the unit memory cell array. Thereafter, when a precharge command is inputted, the bit line pair BL and /BL and the data bus pair SIO and /SIO are again maintained at the precharge voltage VBLP.
As described above, the bit line precharge signal BLEQ is a control signal for maintaining the bit line pair BL and /BL and the data bus pair SIO and /SIO at predetermined voltage levels when the semiconductor memory device is in a precharge mode. The initialization and floating driving of the driving voltage lines are performed using the same bit line precharge signal because the control timing of the driving voltage lines is identical to that of the bit lines.
The bit line precharge signal BLEQ is a signal that swings between a ground voltage VSS and an external voltage VDD or between the ground voltage VSS and a high voltage VPP. When separate driving voltages are used, the following problems may occur. It will be assumed herein that the high voltage VPP is approximately 3.2 V and the external voltage is approximately 1.8 V.
First, when the bit line precharge signal BLEQ swings up to the high voltage level, transistors inside the equalizers and the bit line precharge unit must be implemented with high-voltage transistors, i.e., thick transistors. The high-voltage transistors are used for preventing the damage of the transistors when the bit line precharge signal BLEQ rises up to the high voltage level.
The high-voltage transistors, however, have a limitation in that their precharge performance is degraded. More specifically, the high-voltage transistors generally have a threshold voltage higher than slim transistors and have a low current drivability. Further, when the high voltage is used, a level shifter is used for increasing the voltage level. Hence, a transfer timing of the bit line precharge signal BLEQ is delayed. When the level shifter is used, the transfer timing of the bit line precharge signal BLEQ is delayed by approximately 300 ps.
Meanwhile, when the bit line precharge signal BLEQ swings up to the external voltage level, the transistors inside the equalizers and the bit line precharge unit are implemented with slim transistors.
However, a speed when the bit line precharge signal BLEQ rises to a logic high level becomes slow. The reason for this is that the external voltage is relatively lower than the high voltage.
When a semiconductor memory device operating at a low power supply voltage VDD performs a bank interleave operation, an activation timing of the bit line precharge signal BLEQ may be delayed. In case where while driving the bit line sense amplifier array within a bank, a precharge command is inputted to another bank by the bank interleave operation, the bit line precharge signal BLEQ for performing the precharge operation on another bank is not stably generated because a large amount of external voltage is consumed in driving the bit line sense amplifier in the bank. In other words, because the external voltage is dropped due to the driving of the bit line sense amplifier, a stable external voltage cannot be obtained in generating the bit line precharge signal BLEQ.
When a stable precharge operation is not performed, the bit line pair has an abnormal level in a subsequent driving and thus data fail occurs.